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ISE 8.1 이상버전에서는

Clock 신호를 일반 I/O PAD 에 연결하면 아래와 같은 메시지를 출력하면서 Error 가 발생한다

"ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock
IOB site The clock IOB component <CLK> is placed at site IOB_X1Y84. The
clock IO site can use the fast path between the IO and the Clock buffer/GCLK
if the IOB is placed in the master Clock IOB Site. If this sub optimal
condition is acceptable for this design you may set the environment variable
XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and
allow your design to continue."

해결 방법은 환경변수에 XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING  값을 1로 넣으면 된다

If the increased delay associated with the use of general routing resources is acceptable, the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING environment variable can be set to reduce this error to a warning:

Windows
SET XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING=1

Linux and Solaris
setenv XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING 1

출처 : http://www.xilinx.com/support/answers/21724.htm

라고 햇는데..그래도 해결 안되는이유는????